IC Flip-Flop Dual JK 74LS73

AED 8.30



The 74LS73 is a dual JK flip-flop integrated circuit (IC) that. This IC offers two individual JK flip-flops, making it a valuable component in various applications where synchronized data storage and signal processing are required.



  • Dual JK Flip-Flops: The 74LS73 integrates two JK flip-flops in a single package, allowing for efficient storage and manipulation of binary data.
  • Positive-Edge Triggered: These flip-flops are positive-edge triggered, meaning they respond to the rising edge of clock signals.
  • Data Inputs: The IC features J (data) and K (complement) inputs for each flip-flop, enabling flexible data manipulation.
  • Clear Inputs: Clear inputs (CLR) for both flip-flops allow for the synchronous clearing of stored data.
  • Asynchronous Set Inputs: Set inputs (SET) provide the ability to set the Q outputs independently.
  • Direct Cascading: The 74LS73 supports easy cascading with other 74LS series ICs, facilitating the expansion of sequential logic circuits.
  • Low Power Consumption: This IC is designed with low power consumption in mind, making it suitable for battery-powered devices.
  • Wide Operating Voltage Range: It can operate within a wide voltage range, typically from 4.75V to 5.25V, making it compatible with various digital systems.



  • Supply Voltage (Vcc): Typically 5V
  • Number of Flip-Flops: 2
  • Clock Input (CLK): Positive-Edge Triggered
  • Data Input (J, K): 2 for Each Flip-Flop
  • Clear Input (CLR): 2 (Synchronous Clear)
  • Set Input (SET): 2 (Asynchronous Set)
  • Propagation Delay: Approximately 25ns
  • Operating Temperature Range: -40°C to 85°C
  • Package Type: Dual-In-Line Package (DIP)