AED 7.00
Description
The CD4013 dual D flip-flop is a monolithic complementary MOS (CMOS) integrated circuit made up of N and P channel enhancement mode transistors. Each flip-flop has its own data, set, reset, and clock inputs, as well as its own "Q" and "Q" outputs. Being a CMOS IC, the CD4017 consumes less power than its TTL counterpart. It can operate from 3 V to 18 V while its input pins can tolerate + 0.5 V of its supply voltage. These devices may be used for shift register applications as well as counter and toggle applications by connecting the "Q" output to the data input. During the positive-going transition of the clock pulse, the logic level at the "D" input is transferred to the Q output. Setting or resetting is done independently of the clock by a high level on the set or resets line, respectively.
What is a D Flip-Flop?
A D flip-flop is a circuit that can hold one bit of information. It can have a HIGH or a LOW output. When the clock switches from LOW to HIGH, the output changes to whatever is on the data (D) input. On the rising edge of the clock is another term for it.
Specifications:
- Wide supply voltage range: 3.0V to 15V
- High noise immunity: 0.45 VDD
- Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS
- Type: DIP.
Pinout of the CD4013:
| Pin Name | Pin # | Type | Description |
|---|---|---|---|
| VDD | 14 | Power | Supply Voltage (+3 to +15V) |
| GND | 7 | Power | Ground (0V) |
| Q1, Q2 | 1, 13 | Output | Outputs from the two D Flip-Flops |
| Q1, Q2 | 2, 12 | Output | Inverted outputs from the two D Flip-Flops |
| CLK1, CLK2 | 3, 11 | Input | Clock input for the two D Flip-Flops (Rising Edge) |
| D1, D2 | 5, 9 | Input | D (data) input for the two D Flip-Flops |
| S1, S2 | 6, 8 | Input | Preset the Flip-Flop output to 1 |
| C1, C2 | 4, 10 | Input | Reset the Flip-Flop output to 0 |
Applications
- Automotive
- Alarm system
- Data terminals
- Industrial electronics
- Instrumentation
- Remote metering
- Medical electronics
- Computers
For More Info: Data Sheet