The D-type flip-flop is a modified set-reset flip-flop with an extra inverter to keep the S and R inputs from being at the same logic level using two D flip flop in the same package. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. the positive edge of a clock pulse, the flip flop is activated. The status of the data pin (D) is collected and kept as the output when the clock pin (CLK) turns high (Q). Q will not change again until the next time the clock rises, regardless of how long the clock remains high or if D changes.
1. Output Drive Capability: 10 LSTTL Loads
2. Outputs Directly Interface to CMOS, NMOS, and TTL
3. Operating Voltage Range: 2.0 to 6.0 V
4. Low Input Current: 1.0 A
5. High Noise Immunity Characteristic of CMOS Devices
6. In Compliance with the JEDEC Standard No. 7A Requirements
1 x IC Flip-Flop 2Bit D-Type 74HC74
The Truth table for the D-type flip-flop
|↓ » 0
|↑ » 1
|Reset Q » 0
|↑ » 1
|Set Q » 1
How Does D FlipFlop Work:
The device has had preset and clear inputs, which will drive Q high or low, but they are not utilized in this instance. Because preset and clear are actuated by a low signal, they are connected to Vcc to keep them pushed high. The IC additionally has a negative output (not Q) that is always the inverse of Q. This example does not make use of it.
In this case, the SN74HC74 is quite simple to operate; all that is necessary are clock and data signals. The flip flop, on the other hand, is particularly sensitive to noise since it is connected to a specific rising edge of the clock signal. In this instance, a mechanical switch is employed instead of a real electrical closure.