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Description
CD40103 is an 8-bit synchronous down counter from the CMOS logic family. It has a single output pin that is CO/ZD. When the counter reaches zero, this pin outputs a high value. It has two control inputs and one output that can be Carried out or Zero Detect. These are all active-low logic inputs and outputs. In both synchronous and ripple modes, it can be cascaded.
Specifications:
- Synchronous or asynchronous preset
- Operates at medium speed with a clock frequency (fCL)= 3.6 MHz at VDD= 10V
- Can be cascaded for designing more than an 8-bit counter
- The maximum value of input current at 18V = 1 µA
- Wide voltage supply range of 3 to 15V with different noise margins according to temperature
- One output can drive up to 50 inputs.
- Inputs are provided with diodes protection which interfaces inputs to voltages by using current limiting resistors when Vcc is in excess.
- Standardized, symmetrical output characteristics
- Parametric ratings: 5V, 12V and 15V
Package Includes:
1 x IC Synchronous Binary Down Counter 8-Bit CD40103 BP
Pinout of the CD40103:
It has 16 pins in total This table lists all pins along with their functions.
| Pin Name | Description |
|---|---|
| CLOCK | Enabling and Disabling of the clock signal. |
| CLEAR | Clear the counter to its maximum count. |
| CARRY-IN/COUNTER ENABLE | It is a carry-input pin also known as a counter enable pin. When this input pin is HIGH, the counter stops counting. |
| J0, J1, …, J7 | Jam inputs representing an 8-bit binary word |
| VDD | Connect with Positive terminal of power supply |
| Vss | Connect with Ground terminal |
| CARRY-OUT/ZERO-DEFECT | Output pin whose value would be LOW remains in the same state for one complete clock cycle if carry-in input is active low |
| SYNCHRONOUS PRESET-ENABLE | Preset the counter synchronously. |
| ASYNCHRONOUS PRESET-ENABLE | Preset the counter asynchronously |
How CD40103 Down Counter Can Be Used?
On every positive edge of a clock signal, the value in the counter decrements by one. The counter is reset to its maximum value of 255 in decimal. In this scenario, the CD40103 down counter ignores any input pin signal. In addition, when the CLEAR input is low. It has two pre-set enable options.
If the synchronous preset-enable pin's digital state is active low, the input signal at the carrying input pin becomes don't care. As a result, whenever the clock's positive edge occurs, data accessible on pins J0-J7 is sent to a counter. When the asynchronous preset-enable input pin is low, data from the JAM inputs is fed into the counter asynchronously, regardless of the condition of the clock signal, carry-input, or synchronously preset enable pin.